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CVS: cvs.openbsd.org: src

Module name:	src
Changes by:	miod_(_at_)_cvs_(_dot_)_openbsd_(_dot_)_org	2009/05/25 11:10:40

Modified files:
	sys/arch/mips64/mips64: tlbhandler.S 
	sys/arch/sgi/sgi: machdep.c 

Log message:
Years ago, I fixed an R5000 O2 instability by implementing a workaround for
a chip bug, which was supposed to be fixed in that particular revision of
the die but wasn't (tlbhandler.S 1.16).

Being lazy, I did not write a runtime selection of the appropriate TLB
handler code, although this was on my list.

It turns out that this fix confuses the hell of R10000 processors revision 3
(but not earlier 2.x revisions), to the point of making the Origin 200 here
hang so hard it would not even enter the NMI handler (don't ask me how I
figured this was the cause).

So it's time to choose the appropriate TLB handling flavour at runtime,
building the trampoline code from the fixed exception handler location
jumping to the handler address at runtime. As a bonus, kernels linked in
KSEG0 get the address computation optimized and thus a smaller trampoline
than before.

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