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make woes...

Each time I read more of make's code, I cringe.

I've now looked at the behavior of target redefinitions.

	echo "one"

	echo "two"

You will get "one" out of this Makefile.
The redefinition of a is quite simply ignored, not even with a warning.
On the other hand:


	echo "two"

will yield "two", as the first definition does not have any commands, hence
does not trigger the same mechanism. This is obviously useful, since `pure'
dependency lines should not be mistaken with actual rules.  But it gets

a:	b

.if target(a)
	echo "one"
	echo "two"

yields "one", i.e., a simple dependency line without commands is enough
to let make assert 'yep, I've seen that target alright'.

All of this is really problematic in connection with /usr/share/mk macros.
- setting up a dependency somewhere will be enough to eradicate an 
.if !target()  guard
- forgetting an .if !target() guard will not even trigger a warning. And
you can't even make sure the target was not defined in the Makefile proper.

It's probably possible to fix make, though:
* a true target redefinition (e.g., recipe with rules to apply) should at
least trigger a warning,
* the .if target() test should probably NOT take simple dependencies into
account, for sheer consistency.  Just because you wrote 
a: b
does probably not mean you want to get rid of the default a rule
(especially since it's very easy to write
a: b
if this is what you want)

Opinions ?

	Marc Espie		
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| `real programmers don't die, they just get out of beta'