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kernel/1450: Bug in tx enet driver [patch]
>Number: 1450
>Category: kernel
>Synopsis: Bug in tx enet driver [patch]
>Confidential: no
>Severity: non-critical
>Priority: medium
>Responsible: bugs
>State: open
>Class: sw-bug
>Submitter-Id: net
>Arrival-Date: Sat Oct 14 21:30:02 MDT 2000
>Last-Modified:
>Originator: Dylan Adams
>Organization:
net
>Release: 2.8-current
>Environment:
System : OpenBSD 2.8
Architecture: OpenBSD.i386
Machine : i386 (K7 700)
>Description:
The tx ethernet driver was lacking a delay loop which would cause the driver to hang on startup. It was also significantly out of date with the FreeBSD verson, which had many improvements including mii support.
>How-To-Repeat:
Insert card. Boot. Whince. Repeat. Turn of all caches, crippling machine, but allowing it to boot. Fix buggy driver.
>Fix:
This patch was made with 'cvs diff if_tx.c if_txvar.h files.pci > if_tx.patch'. I hope it's in the right format.
if_tx.c patched to be in sync w/ FreeBSD and fix bug
if_txvar.c patched to fix what the FreeBSD guys broke
files.pci patched because if_tx is now dependant on mii (and ~100 lines shorter)
Index: if_tx.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/if_tx.c,v
retrieving revision 1.10
diff -r1.10 if_tx.c
1,2c1,2
< /* $OpenBSD: if_tx.c,v 1.10 2000/02/21 20:54:04 jason Exp $ */
< /* $FreeBSD: src/sys/pci/if_tx.c,v 1.34 1999/12/21 11:14:10 eivind Exp $ */
---
> /* $OpenBSD: if_tx.c,v 1.9.2.1 2000/02/21 22:29:13 niklas Exp $ */
> /* $FreeBSD: src/sys/pci/if_tx.c,v 1.40 2000/07/13 22:54:34 archie Exp $ */
38c38,39
< * Test, test and test again:-(
---
> * Refactor out Free/Open compat cruft
> * Modularize, Modularize, and Modularize some more
43,44d43
< /*#define EPIC_NOIFMEDIA 1*/
< /*#define EPIC_USEIOSPACE 1*/
48,69d46
< #if defined(EPIC_DEBUG)
< #define dprintf(a) printf a
< #else
< #define dprintf(a)
< #endif
<
< /* Macro to get either mbuf cluster or nothing */
< #define EPIC_MGETCLUSTER(m) \
< { MGETHDR((m),M_DONTWAIT,MT_DATA); \
< if (m) { \
< MCLGET((m),M_DONTWAIT); \
< if( 0 == ((m)->m_flags & M_EXT) ){ \
< m_freem(m); \
< (m) = NULL; \
< } \
< } \
< }
<
< #include "bpfilter.h"
< #include "pci.h"
<
< #if NPCI > 0
71a49
> #include <sys/sockio.h>
76c54,88
< #include <sys/sockio.h>
---
> #include <sys/queue.h>
>
> #if defined(__FreeBSD__)
> #define NBPFILTER 1
>
> #include <net/if.h>
> #include <net/if_arp.h>
> #include <net/ethernet.h>
> #include <net/if_media.h>
>
> #include <net/bpf.h>
>
> #include <vm/vm.h> /* for vtophys */
> #include <vm/pmap.h> /* for vtophys */
> #include <machine/clock.h> /* for DELAY */
> #include <machine/bus_memio.h>
> #include <machine/bus_pio.h>
> #include <machine/bus.h>
> #include <machine/resource.h>
> #include <sys/bus.h>
> #include <sys/rman.h>
>
> #include <pci/pcireg.h>
> #include <pci/pcivar.h>
>
> #include <dev/mii/mii.h>
> #include <dev/mii/miivar.h>
>
> #include "miibus_if.h"
>
> #include <pci/if_txvar.h>
> #else /* __OpenBSD__ */
> #include "bpfilter.h"
>
> #include <sys/device.h>
81,84d92
<
< #if !defined(SIOCSIFMEDIA) || defined(EPIC_NOIFMEDIA)
< #define EPIC_NOIFMEDIA 1
< #else
86d93
< #endif
92a100
> #include <netinet/if_ether.h>
107d114
< #include <net/bpfdesc.h>
110,116d116
< #if defined(__OpenBSD__)
< #include <sys/ioctl.h>
< #include <sys/errno.h>
< #include <sys/device.h>
<
< #include <netinet/if_ether.h>
<
117a118,121
> #include <vm/pmap.h>
>
> #include <dev/mii/mii.h>
> #include <dev/mii/miivar.h>
124,133d127
< #else /* __FreeBSD__ */
< #include <net/if_mib.h>
< #include <netinet/in.h>
< #include <netinet/if_ether.h>
< #include <vm/vm.h>
< #include <vm/pmap.h>
< #include <machine/clock.h>
<
< #include <pci/pcivar.h>
< #include <pci/if_txvar.h>
137,140c131
< #if __FreeBSD_version >= 300000
< #define EPIC_IFIOCTL_CMD_TYPE u_long
< #else
< #define EPIC_IFIOCTL_CMD_TYPE int
---
> MODULE_DEPEND(tx, miibus, 1, 1, 1);
141a133,134
>
> #if defined(__FreeBSD__)
144d136
< #define EPIC_IFIOCTL_CMD_TYPE u_long
148,198c140,177
< int epic_ifioctl __P((register struct ifnet *, EPIC_IFIOCTL_CMD_TYPE, caddr_t));
< EPIC_INTR_RET_TYPE epic_intr __P((void *));
< int epic_common_attach __P((epic_softc_t *));
< void epic_ifstart __P((struct ifnet *));
< void epic_ifwatchdog __P((struct ifnet *));
< int epic_init __P((epic_softc_t *));
< void epic_stop __P((epic_softc_t *));
< void epic_rx_done __P((epic_softc_t *));
< void epic_tx_done __P((epic_softc_t *));
< int epic_init_rings __P((epic_softc_t *));
< void epic_free_rings __P((epic_softc_t *));
< void epic_stop_activity __P((epic_softc_t *));
< void epic_start_activity __P((epic_softc_t *));
< void epic_set_rx_mode __P((epic_softc_t *));
< void epic_set_tx_mode __P((epic_softc_t *));
< void epic_set_mc_table __P((epic_softc_t *));
< void epic_set_media_speed __P((epic_softc_t *));
< void epic_init_phy __P((epic_softc_t *));
< void epic_dump_state __P((epic_softc_t *));
< int epic_autoneg __P((epic_softc_t *));
< int epic_read_eeprom __P((epic_softc_t *,u_int16_t));
< void epic_output_eepromw __P((epic_softc_t *, u_int16_t));
< u_int16_t epic_input_eepromw __P((epic_softc_t *));
< u_int8_t epic_eeprom_clock __P((epic_softc_t *,u_int8_t));
< void epic_write_eepromreg __P((epic_softc_t *,u_int8_t));
< u_int8_t epic_read_eepromreg __P((epic_softc_t *));
< u_int16_t epic_read_phy_register __P((epic_softc_t *, u_int16_t));
< void epic_write_phy_register __P((epic_softc_t *, u_int16_t, u_int16_t));
< #if 0
< void epic_dump_phy_regs __P((epic_softc_t *));
< #endif
<
< #if !defined(EPIC_NOIFMEDIA)
< int epic_ifmedia_change __P((struct ifnet *));
< void epic_ifmedia_status __P((struct ifnet *, struct ifmediareq *));
< #endif
<
< int epic_mtypes [] = {
< IFM_ETHER | IFM_10_T,
< IFM_ETHER | IFM_10_T | IFM_FDX,
< IFM_ETHER | IFM_100_TX,
< IFM_ETHER | IFM_100_TX | IFM_FDX,
< IFM_ETHER | IFM_10_T | IFM_LOOP,
< IFM_ETHER | IFM_10_T | IFM_FDX | IFM_LOOP,
< IFM_ETHER | IFM_10_T | IFM_LOOP | IFM_FLAG1,
< IFM_ETHER | IFM_100_TX | IFM_LOOP,
< IFM_ETHER | IFM_100_TX | IFM_LOOP | IFM_FLAG1,
< IFM_ETHER | IFM_100_TX | IFM_FDX | IFM_LOOP,
< IFM_ETHER | IFM_AUTO
< };
< #define EPIC_MTYPESNUM (sizeof(epic_mtypes) / sizeof(epic_mtypes[0]))
---
> #if defined(__FreeBSD__)
> #define EPIC_MIIBUS_WRITEREG_RET_TYPE int
> #else /* __OpenBSD__ */
> #define EPIC_MIIBUS_WRITEREG_RET_TYPE void
> #endif
>
>
> static int epic_ifioctl __P((register struct ifnet *, u_long, caddr_t));
> static EPIC_INTR_RET_TYPE epic_intr __P((void *));
> static int epic_common_attach __P((epic_softc_t *));
> static void epic_ifstart __P((struct ifnet *));
> static void epic_ifwatchdog __P((struct ifnet *));
> static int epic_init __P((epic_softc_t *));
> static void epic_reset __P((epic_softc_t *));
> static void epic_stop __P((epic_softc_t *));
> static void epic_rx_done __P((epic_softc_t *));
> static void epic_tx_done __P((epic_softc_t *));
> static int epic_init_rings __P((epic_softc_t *));
> static void epic_free_rings __P((epic_softc_t *));
> static void epic_stop_activity __P((epic_softc_t *));
> static void epic_start_activity __P((epic_softc_t *));
> static void epic_set_rx_mode __P((epic_softc_t *));
> static void epic_set_tx_mode __P((epic_softc_t *));
> static void epic_set_mc_table __P((epic_softc_t *));
> static int epic_read_eeprom __P((epic_softc_t *,u_int16_t));
> static void epic_output_eepromw __P((epic_softc_t *, u_int16_t));
> static u_int16_t epic_input_eepromw __P((epic_softc_t *));
> static u_int8_t epic_eeprom_clock __P((epic_softc_t *,u_int8_t));
> static void epic_write_eepromreg __P((epic_softc_t *,u_int8_t));
> static u_int8_t epic_read_eepromreg __P((epic_softc_t *));
>
> static int epic_read_phy_reg __P((epic_softc_t *, int, int));
> static void epic_write_phy_reg __P((epic_softc_t *, int, int, int));
>
> static int epic_miibus_readreg __P((struct device*, int, int));
> static void epic_miibus_statchg __P((struct device *));
>
> static EPIC_MIIBUS_WRITEREG_RET_TYPE epic_miibus_writereg __P((struct device*, int, int, int));
199a179,180
> static int epic_ifmedia_upd __P((struct ifnet *));
> static void epic_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
210c191
< void epic_shutdown __P((void *));
---
> void epic_openbsd_shutdown __P((void *));
230c211
< if( PCI_PRODUCT(pa->pa_id) == CHIPID_83C170 )
---
> if( PCI_PRODUCT(pa->pa_id) == SMC_DEVICEID_83C170 )
250d230
< int i;
252,254d231
< #if !defined(EPIC_NOIFMEDIA)
< int tmp;
< #endif
257,258c234
< command |= PCI_COMMAND_IO_ENABLE |
< PCI_COMMAND_MEM_ENABLE |
---
> command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
259a236
>
265c242
< printf(": failed to enable memory mapping\n");
---
> printf(": failed to enable I/O ports\n");
268c245
< if( pci_io_find(pc, pa->pa_tag, PCI_CBIO, &iobase, &iosize)) {
---
> if( pci_io_find(pc, pa->pa_tag, PCI_BASEIO, &iobase, &iosize)) {
282c259
< if( pci_mem_find(pc, pa->pa_tag, PCI_CBMA, &iobase, &iosize, NULL)) {
---
> if( pci_mem_find(pc, pa->pa_tag, PCI_BASEMEM, &iobase, &iosize, NULL)) {
292a270,272
> /*
> * Set up if
> */
294c274
< bcopy(sc->sc_dev.dv_xname, ifp->if_xname,IFNAMSIZ);
---
> bcopy(sc->dev.dv_xname, ifp->if_xname, IFNAMSIZ);
301c281,283
< /* Do common attach procedure */
---
> /*
> * Do common attach procedure
> */
304c286,288
< /* Map interrupt */
---
> /*
> * Map interrupt
> */
323,365c307
< printf(" address %s",ether_sprintf(sc->sc_macaddr));
< /* Read current media config and display it too */
< i = PHY_READ_2( sc, DP83840_BMCR );
< #if !defined(EPIC_NOIFMEDIA)
< tmp = IFM_ETHER;
< #endif
< if( i & BMCR_AUTONEGOTIATION ){
< printf(", Auto-Neg ");
<
< /* To avoid bug in QS6612 read LPAR enstead of BMSR */
< i = PHY_READ_2( sc, DP83840_LPAR );
< if( i & (ANAR_100_TX|ANAR_100_TX_FD) ) printf("100Mbps");
< else printf("10Mbps");
< if( i & (ANAR_10_FD|ANAR_100_TX_FD) ) printf(" FD");
< #if !defined(EPIC_NOIFMEDIA)
< tmp |= IFM_AUTO;
< #endif
< } else {
< #if defined(EPIC_NOIFMEDIA)
< ifp->if_flags |= IFF_LINK0;
< #endif
< if( i & BMCR_100MBPS ) {
< printf(", 100Mbps");
< #if !defined(EPIC_NOIFMEDIA)
< tmp |= IFM_100_TX;
< #else
< ifp->if_flags |= IFF_LINK2;
< #endif
< } else {
< printf(", 10Mbps");
< #if !defined(EPIC_NOIFMEDIA)
< tmp |= IFM_10_T;
< #endif
< }
< if( i & BMCR_FULL_DUPLEX ) {
< printf(" FD");
< #if !defined(EPIC_NOIFMEDIA)
< tmp |= IFM_FDX;
< #else
< ifp->if_flags |= IFF_LINK1;
< #endif
< }
< }
---
> printf(" address %s\n",ether_sprintf(sc->sc_macaddr));
367,369c309,312
< /* Init ifmedia interface */
< #if !defined(EPIC_NOIFMEDIA)
< ifmedia_init(&sc->ifmedia,0,epic_ifmedia_change,epic_ifmedia_status);
---
> /*
> * ifmedia setup
> */
> ifmedia_init(&sc->miibus.mii_media, 0, epic_ifmedia_upd, epic_ifmedia_sts);
371,372c314,329
< for (i=0; i<EPIC_MTYPESNUM; i++)
< ifmedia_add(&sc->ifmedia,epic_mtypes[i],0,NULL);
---
> /*
> * mii setup
> */
> sc->miibus.mii_ifp = ifp;
> sc->miibus.mii_readreg = epic_miibus_readreg;
> sc->miibus.mii_writereg = epic_miibus_writereg;
> sc->miibus.mii_statchg = epic_miibus_statchg;
>
> mii_phy_probe(self, &sc->miibus, 0xffffffff);
>
> if (LIST_FIRST(&sc->miibus.mii_phys) == NULL) {
> ifmedia_add(&sc->miibus.mii_media, IFM_ETHER|IFM_NONE,0,NULL);
> ifmedia_set(&sc->miibus.mii_media, IFM_ETHER|IFM_NONE);
> } else {
> ifmedia_set(&sc->miibus.mii_media, IFM_ETHER|IFM_AUTO);
> }
374,375d330
< ifmedia_set(&sc->ifmedia, tmp);
< #endif
386,387c341
< shutdownhook_establish(epic_shutdown, sc);
< printf("\n");
---
> shutdownhook_establish(epic_openbsd_shutdown, sc);
390c344,346
< /* Simple call epic_stop() */
---
> /*
> * Simply call epic_stop()
> */
392c348
< epic_shutdown(
---
> epic_openbsd_shutdown(
401,412c357,398
< const char* epic_freebsd_probe __P((pcici_t, pcidi_t));
< void epic_freebsd_attach __P((pcici_t, int));
< void epic_shutdown __P((int, void *));
<
< /* Global variables */
< u_long epic_pci_count;
< struct pci_device txdevice = {
< "tx",
< epic_freebsd_probe,
< epic_freebsd_attach,
< &epic_pci_count,
< NULL
---
> static int epic_freebsd_probe __P((struct device*));
> static int epic_freebsd_attach __P((struct device*));
> static void epic_freebsd_shutdown __P((struct device*));
> static int epic_freebsd_detach __P((struct device*));
> static struct epic_type *epic_devtype __P((struct device*));
> static void epic_miibus_mediainit __P((struct device*));
>
> static device_method_t epic_methods[] = {
> /* Device interface */
> DEVMETHOD(device_probe, epic_freebsd_probe),
> DEVMETHOD(device_attach, epic_freebsd_attach),
> DEVMETHOD(device_detach, epic_freebsd_detach),
> DEVMETHOD(device_shutdown, epic_freebsd_shutdown),
>
> /* bus interface */
> DEVMETHOD(bus_print_child, bus_generic_print_child),
> DEVMETHOD(bus_driver_added, bus_generic_driver_added),
>
> /* MII interface */
> DEVMETHOD(miibus_readreg, epic_miibus_readreg),
> DEVMETHOD(miibus_writereg, epic_miibus_writereg),
> DEVMETHOD(miibus_statchg, epic_miibus_statchg),
> DEVMETHOD(miibus_mediainit, epic_miibus_mediainit),
>
> { 0, 0 }
> };
>
> static driver_t epic_driver = {
> "tx",
> epic_methods,
> sizeof(epic_softc_t)
> };
>
> static devclass_t epic_devclass;
>
> DRIVER_MODULE(if_tx, pci, epic_driver, epic_devclass, 0, 0);
> DRIVER_MODULE(miibus, tx, miibus_driver, miibus_devclass, 0, 0);
>
> static struct epic_type epic_devs[] = {
> { SMC_VENDORID, SMC_DEVICEID_83C170,
> "SMC EtherPower II 10/100" },
> { 0, 0, NULL }
415,416c401,415
< /* Append this driver to pci drivers list */
< COMPAT_PCI_DRIVER (tx, txdevice);
---
> static int
> epic_freebsd_probe(dev)
> struct device* dev;
> {
> struct epic_type *t;
>
> t = epic_devtype(dev);
>
> if (t != NULL) {
> device_set_desc(dev, t->name);
> return(0);
> }
>
> return(ENXIO);
> }
418,422c417,419
< /* Synopsis: Check if device id corresponds with SMC83C170 id. */
< const char*
< epic_freebsd_probe(
< pcici_t config_id,
< pcidi_t device_id)
---
> static struct epic_type *
> epic_devtype(dev)
> struct device* dev;
424,425c421
< if( PCI_VENDORID(device_id) != SMC_VENDORID )
< return NULL;
---
> struct epic_type *t;
427,428c423
< if( PCI_CHIPID(device_id) == CHIPID_83C170 )
< return "SMC 83c170";
---
> t = epic_devs;
430c425,432
< return NULL;
---
> while(t->name != NULL) {
> if ((pci_get_vendor(dev) == t->ven_id) &&
> (pci_get_device(dev) == t->dev_id)) {
> return(t);
> }
> t++;
> }
> return (NULL);
432a435,442
> #if defined(EPIC_USEIOSPACE)
> #define EPIC_RES SYS_RES_IOPORT
> #define EPIC_RID PCIR_BASEIO
> #else
> #define EPIC_RES SYS_RES_MEMORY
> #define EPIC_RID PCIR_BASEMEM
> #endif
>
437,440c447,449
< void
< epic_freebsd_attach(
< pcici_t config_id,
< int unit)
---
> static int
> epic_freebsd_attach(dev)
> struct device* dev;
444,448d452
< #if defined(EPIC_USEIOSPACE)
< u_int32_t iobase;
< #else
< caddr_t pmembase;
< #endif
450c454,455
< int i,s,tmp;
---
> int unit, error;
> int i, s, rid, tmp;
452c457
< printf("tx%d",unit);
---
> s = splimp ();
454,456c459,460
< /* Allocate memory for softc, hardware descriptors and frag lists */
< sc = (epic_softc_t *) malloc( sizeof(epic_softc_t), M_DEVBUF, M_NOWAIT);
< if (sc == NULL) return;
---
> sc = device_get_softc(dev);
> unit = device_get_unit(dev);
460a465
> sc->dev = dev;
468a474
> ifp->if_output = ether_output;
473,474c479,486
< ifp->if_output = ether_output;
< ifp->if_snd.ifq_maxlen = TX_RING_SIZE;
---
> ifp->if_baudrate = 10000000;
> ifp->if_snd.ifq_maxlen = TX_RING_SIZE - 1;
>
> /* Enable ports, memory and busmastering */
> command = pci_read_config(dev, PCIR_COMMAND, 4);
> command |= PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
> pci_write_config(dev, PCIR_COMMAND, command, 4);
> command = pci_read_config(dev, PCIR_COMMAND, 4);
476d487
< /* Get iobase or membase */
478,486c489,498
< command = PCI_CONF_READ(PCI_CFCS);
< command |= PCI_CFCS_IOEN;
< PCI_CONF_WRITE(PCI_CFCS, command);
< command = PCI_CONF_READ(PCI_CFCS);
<
< if (!(command & PCI_CFCS_IOEN)) {
< printf(": failed to enable memory mapping!\n");
< free(sc, M_DEVBUF);
< return;
---
> if (!(command & PCIM_CMD_PORTEN)) {
> device_printf(dev, "failed to enable I/O mapping!\n");
> error = ENXIO;
> goto fail;
> }
> #else
> if (!(command & PCIM_CMD_MEMEN)) {
> device_printf(dev, "failed to enable memory mapping!\n");
> error = ENXIO;
> goto fail;
487a500
> #endif
489,492c502,509
< if (!pci_map_port(config_id, PCI_CBIO,(u_short *) &(sc->iobase))) {
< printf(": cannot map port\n");
< free(sc, M_DEVBUF);
< return;
---
> rid = EPIC_RID;
> sc->res = bus_alloc_resource(dev, EPIC_RES, &rid, 0, ~0, 1,
> RF_ACTIVE);
>
> if (sc->res == NULL) {
> device_printf(dev, "couldn't map ports/memory\n");
> error = ENXIO;
> goto fail;
494,503c511,524
< #else
< command = PCI_CONF_READ(PCI_CFCS);
< command |= PCI_CFCS_MAEN;
< PCI_CONF_WRITE(PCI_CFCS, command);
< command = PCI_CONF_READ(PCI_CFCS);
<
< if (!(command & PCI_CFCS_MAEN)) {
< printf(": failed to enable memory mapping!\n");
< free(sc, M_DEVBUF);
< return;
---
>
> sc->sc_st = rman_get_bustag(sc->res);
> sc->sc_sh = rman_get_bushandle(sc->res);
>
> /* Allocate interrupt */
> rid = 0;
> sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
> RF_SHAREABLE | RF_ACTIVE);
>
> if (sc->irq == NULL) {
> device_printf(dev, "couldn't map interrupt\n");
> bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
> error = ENXIO;
> goto fail;
506,509c527,534
< if (!pci_map_mem(config_id, PCI_CBMA,(vm_offset_t *) &(sc->csr),(vm_offset_t *) &pmembase)) {
< printf(": cannot map memory\n");
< free(sc, M_DEVBUF);
< return;
---
> error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET,
> epic_intr, sc, &sc->sc_ih);
>
> if (error) {
> bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
> bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
> device_printf(dev, "couldn't set up irq\n");
> goto fail;
511d535
< #endif
513,514c537,548
< /* Do OS independent part, including chip wakeup and reset */
< if( epic_common_attach(sc) ) return;
---
> /*
> * Do ifmedia setup.
> */
> if (mii_phy_probe(dev, &sc->miibus,
> epic_ifmedia_upd, epic_ifmedia_sts)) {
> device_printf(dev, "MII without any PHY!?\n");
> bus_teardown_intr(dev, sc->irq, sc->sc_ih);
> bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
> bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
> error = ENXIO;
> goto fail;
> }
516,518c550,558
< command = PCI_CONF_READ(PCI_CFCS);
< command |= PCI_CFCS_BMEN;
< PCI_CONF_WRITE(PCI_CFCS, command);
---
> /* Do OS independent part, including chip wakeup and reset */
> if (epic_common_attach(sc)) {
> device_printf(dev, "memory distribution error\n");
> bus_teardown_intr(dev, sc->irq, sc->sc_ih);
> bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
> bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
> error = ENXIO;
> goto fail;
> }
521,523c561
< printf(": address %02x:%02x:%02x:%02x:%02x:%02x,",
< sc->sc_macaddr[0],sc->sc_macaddr[1],sc->sc_macaddr[2],
< sc->sc_macaddr[3],sc->sc_macaddr[4],sc->sc_macaddr[5]);
---
> device_printf(dev, "address %6D,", sc->sc_macaddr, ":");
534a573
> printf ("\n");
536,577c575,577
< /* Read current media config and display it too */
< i = PHY_READ_2( sc, DP83840_BMCR );
< #if !defined(EPIC_NOIFMEDIA)
< tmp = IFM_ETHER;
< #endif
< if( i & BMCR_AUTONEGOTIATION ){
< printf(", Auto-Neg ");
<
< /* To avoid bug in QS6612 read LPAR enstead of BMSR */
< i = PHY_READ_2( sc, DP83840_LPAR );
< if( i & (ANAR_100_TX|ANAR_100_TX_FD) ) printf("100Mbps ");
< else printf("10Mbps ");
< if( i & (ANAR_10_FD|ANAR_100_TX_FD) ) printf("FD");
< #if !defined(EPIC_NOIFMEDIA)
< tmp |= IFM_AUTO;
< #endif
< } else {
< #if defined(EPIC_NOIFMEDIA)
< ifp->if_flags |= IFF_LINK0;
< #endif
< if( i & BMCR_100MBPS ) {
< printf(", 100Mbps ");
< #if !defined(EPIC_NOIFMEDIA)
< tmp |= IFM_100_TX;
< #else
< ifp->if_flags |= IFF_LINK2;
< #endif
< } else {
< printf(", 10Mbps ");
< #if !defined(EPIC_NOIFMEDIA)
< tmp |= IFM_10_T;
< #endif
< }
< if( i & BMCR_FULL_DUPLEX ) {
< printf("FD");
< #if !defined(EPIC_NOIFMEDIA)
< tmp |= IFM_FDX;
< #else
< ifp->if_flags |= IFF_LINK1;
< #endif
< }
< }
---
> /* Attach to OS's managers */
> ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
> callout_handle_init(&sc->stat_ch);
579,581c579,580
< /* Init ifmedia interface */
< #if !defined(EPIC_NOIFMEDIA)
< ifmedia_init(&sc->ifmedia,0,epic_ifmedia_change,epic_ifmedia_status);
---
> fail:
> splx(s);
583,584c582,583
< for (i=0; i<EPIC_MTYPESNUM; i++)
< ifmedia_add(&sc->ifmedia,epic_mtypes[i],0,NULL);
---
> return(error);
> }
586,587c585,594
< ifmedia_set(&sc->ifmedia, tmp);
< #endif
---
> /*
> * Detach driver and free resources
> */
> static int
> epic_freebsd_detach(dev)
> struct device* dev;
> {
> struct ifnet *ifp;
> epic_softc_t *sc;
> int s;
591,596c598,599
< /* Map interrupt */
< if( !pci_map_int(config_id, epic_intr, (void*)sc, &net_imask) ) {
< printf(": couldn't map interrupt\n");
< free(sc, M_DEVBUF);
< return;
< }
---
> sc = device_get_softc(dev);
> ifp = &sc->arpcom.ac_if;
598,599c601
< /* Set shut down routine to stop DMA processes on reboot */
< at_shutdown(epic_shutdown, sc, SHUTDOWN_POST_SYNC);
---
> ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
601,603c603
< /* Attach to if manager */
< if_attach(ifp);
< ether_ifattach(ifp);
---
> epic_stop(sc);
605,607c605,612
< #if NBPFILTER > 0
< bpfattach(ifp,DLT_EN10MB, sizeof(struct ether_header));
< #endif
---
> bus_generic_detach(dev);
> device_delete_child(dev, sc->miibus);
>
> bus_teardown_intr(dev, sc->irq, sc->sc_ih);
> bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
> bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
>
> free(sc->pool, M_DEVBUF);
611c616,641
< printf("\n");
---
> return(0);
> }
>
> #undef EPIC_RES
> #undef EPIC_RID
>
> /*
> *
> */
> static void epic_miibus_mediainit(dev)
> struct device* dev;
> {
> epic_softc_t *sc;
> struct mii_data *mii;
> struct ifmedia *ifm;
> int media;
>
> sc = epic_dev_ptr(dev);
> mii = epic_mii_ptr(sc);
> ifm = &mii->mii_media;
>
> if(CSR_READ_4(sc, MIICFG) & MIICFG_PHY_PRESENT) {
> media = IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, mii->mii_instance);
> printf(EPIC_FORMAT ": serial PHY detected (10Base2/BNC)\n",EPIC_ARGS(sc));
> ifmedia_add(ifm, media, 0, NULL);
> }
615,619c645,651
<
< void
< epic_shutdown(
< int howto,
< void *sc)
---
> /*
> * Stop all chip I/O so that the kernel's probe routines don't
> * get confused by errant DMAs when rebooting.
> */
> static void
> epic_freebsd_shutdown(dev)
> struct device* dev;
620a653,656
> epic_softc_t *sc;
>
> sc = device_get_softc(dev);
>
622d657
< }
623a659,660
> return;
> }
627c664
< OS-independing part
---
> OS-independent part
631a669
> * This is a mess
633,637c671,675
< int
< epic_ifioctl __P((
< register struct ifnet * ifp,
< EPIC_IFIOCTL_CMD_TYPE command,
< caddr_t data))
---
> static int
> epic_ifioctl(ifp, command, data)
> struct ifnet *ifp;
> u_long command;
> caddr_t data;
640a679,682
> #if defined(__FreeBSD__)
> struct mii_data *mii;
> struct ifreq *ifr = (struct ifreq *) data;
> #endif
663c705
< #endif /* __FreeBSD__ */
---
> #endif
686c728
< #endif
---
> #endif /* __FreeBSD__ */
705,706d746
< epic_stop_activity(sc);
<
707a748
> epic_stop_activity(sc);
709,713d749
<
< #if defined(EPIC_NOIFMEDIA)
< /* Handle IFF_LINKx flags */
< epic_set_media_speed(sc);
< #endif
735d770
< #if !defined(EPIC_NOIFMEDIA)
738,739c773,777
< error = ifmedia_ioctl(ifp, (struct ifreq *)data,
< &sc->ifmedia, command);
---
> #if defined(__FreeBSD__)
> mii = device_get_softc(sc->miibus);
> error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
> break;
> #else //__OpenBSD__
753c791
< * and frag lists, wake up chip, read MAC address and PHY identyfier.
---
> * and frag lists, wake up chip, and read MAC address.
756,758c794,796
< int
< epic_common_attach(
< epic_softc_t *sc)
---
> static int
> epic_common_attach(sc)
> epic_softc_t *sc;
762a801,803
> /*
> * Allocate memory for io buffers
> */
765c806
< sizeof(struct epic_tx_desc)*TX_RING_SIZE + PAGE_SIZE,
---
> sizeof(struct epic_tx_desc)*TX_RING_SIZE + PAGE_SIZE;
774c815,817
< /* Align pool on PAGE_SIZE */
---
> /*
> * Align pool on PAGE_SIZE
> */
778c821,823
< /* Distribute memory */
---
> /*
> * Distribute memory
> */
785,789c830,833
< /* Bring the chip out of low-power mode. */
< CSR_WRITE_4( sc, GENCTL, GENCTL_SOFT_RESET);
<
< /* Workaround for Application Note 7-15 */
< for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
---
> /*
> * reset the chip
> */
> epic_reset( sc );
791c835,837
< /* Read mac address from EEPROM */
---
> /*
> * Read mac address from EEPROM
> */
795,800c841,843
< /* Identify PHY */
< sc->phyid = PHY_READ_2(sc, DP83840_PHYIDR1 )<<6;
< sc->phyid|= (PHY_READ_2( sc, DP83840_PHYIDR2 )>>10)&0x3F;
< if( QS6612_OUI != sc->phyid )
< printf(": WARNING! PHY unknown (0x%x)",sc->phyid);
<
---
> /*
> * Set defaults
> */
812,813c855,858
< void
< epic_ifstart(struct ifnet * const ifp){
---
> static void
> epic_ifstart(ifp)
> struct ifnet * ifp;
> {
822,835d866
< #if 0
< /* If no link is established, simply free all mbufs in queue */
< PHY_READ_2( sc, DP83840_BMSR );
< if( !(BMSR_LINK_STATUS & PHY_READ_2( sc, DP83840_BMSR )) ){
< IF_DEQUEUE( &ifp->if_snd, m0 );
< while( m0 ) {
< m_freem(m0);
< IF_DEQUEUE( &ifp->if_snd, m0 );
< }
< return;
< }
< #endif
<
< /* Link is OK, queue packets to NIC */
847,857d877
< /* If descriptor is busy, set IFF_OACTIVE and exit */
< if( desc->status & 0x8000 ) {
< dprintf((EPIC_FORMAT ": desc is busy in ifstart, up and down interface please\n",EPIC_ARGS(sc)));
< break;
< }
<
< if( buf->mbuf ) {
< dprintf((EPIC_FORMAT ": mbuf not freed in ifstart, up and down interface please\n",EPIC_ARGS(sc)));
< break;
< }
<
903,907c923
< #if defined(__FreeBSD__)
< bpf_mtap( ifp, m0 );
< #else /* __OpenBSD__ */
< bpf_mtap( ifp->if_bpf, m0 );
< #endif /* __FreeBSD__ */
---
> bpf_mtap( EPIC_BPFTAP_ARG(ifp), m0 );
918,919c934
< *
< * splimp() invoked before epic_intr_normal()
---
> * Synopsis: Finish all received frames.
921,923c936,938
< void
< epic_rx_done __P((
< epic_softc_t *sc ))
---
> static void
> epic_rx_done(sc)
> epic_softc_t *sc;
970a986
> #if !defined(__FreeBSD__)
974,978c990
< #if defined(__FreeBSD__)
< bpf_mtap( &sc->sc_if, m );
< #else /* __OpenBSD__ */
< bpf_mtap( sc->sc_if.if_bpf, m );
< #endif /* __FreeBSD__ */
---
> bpf_mtap( EPIC_BPFTAP_ARG(&sc->sc_if), m );
979a992
> #endif /* !__FreeBSD__ */
1001,1003c1014,1016
< void
< epic_tx_done __P((
< register epic_softc_t *sc ))
---
> static void
> epic_tx_done(sc)
> epic_softc_t *sc;
1041,1042c1054
< *
< * splimp() assumed to be done
---
> * This is a mess
1044,1046c1056,1058
< EPIC_INTR_RET_TYPE
< epic_intr (
< void *arg)
---
> static EPIC_INTR_RET_TYPE
> epic_intr(arg)
> void *arg;
1054d1065
<
1069,1070d1079
< if( sc->sc_if.if_flags & IFF_DEBUG )
< epic_dump_state(sc);
1085,1124d1093
< if( (status & INTSTAT_GP2) && (QS6612_OUI == sc->phyid) ) {
< u_int32_t phystatus = PHY_READ_2( sc, QS6612_INTSTAT );
<
< if( phystatus & INTSTAT_AN_COMPLETE ) {
< u_int32_t bmcr;
< if( epic_autoneg(sc) == EPIC_FULL_DUPLEX ) {
< dprintf((EPIC_FORMAT ": going fullduplex\n",EPIC_ARGS(sc)));
< bmcr = BMCR_FULL_DUPLEX | PHY_READ_2( sc, DP83840_BMCR );
< sc->txcon |= TXCON_FULL_DUPLEX;
< } else {
< /* Default to half-duplex */
< dprintf((EPIC_FORMAT ": going halfduplex\n",EPIC_ARGS(sc)));
< bmcr = ~BMCR_FULL_DUPLEX & PHY_READ_2( sc, DP83840_BMCR );
< sc->txcon &= ~TXCON_FULL_DUPLEX;
< }
<
< /* There is apparently QS6612 chip bug: */
< /* BMCR_FULL_DUPLEX flag is not updated by */
< /* autonegotiation process, so update it by hands */
< /* so we can rely on it in epic_ifmedia_status() */
< PHY_WRITE_2( sc, DP83840_BMCR, bmcr );
<
< epic_stop_activity(sc);
< epic_set_tx_mode(sc);
< epic_start_activity(sc);
< }
<
< PHY_READ_2(sc, DP83840_BMSR);
< if( !(PHY_READ_2(sc, DP83840_BMSR) & BMSR_LINK_STATUS) ) {
< dprintf((EPIC_FORMAT ": WARNING! link down\n",EPIC_ARGS(sc)));
< sc->flags |= EPIC_LINK_DOWN;
< } else {
< dprintf((EPIC_FORMAT ": link up\n",EPIC_ARGS(sc)));
< sc->flags &= ~EPIC_LINK_DOWN;
< }
<
< /* We should clear GP2 int again after we clear it on PHY */
< CSR_WRITE_4( sc, INTSTAT, INTSTAT_GP2 );
< }
<
1138,1139d1106
< epic_dump_state(sc);
<
1183,1184d1149
< *
< * splimp() invoked here
1186,1188c1151,1153
< void
< epic_ifwatchdog __P((
< struct ifnet *ifp))
---
> static void
> epic_ifwatchdog(ifp)
> struct ifnet *ifp;
1203,1205c1168
< #if defined(EPIC_DEBUG)
< if( ifp->if_flags & IFF_DEBUG ) epic_dump_state(sc);
< #endif
---
>
1222,1225c1185,1190
< #if defined(SIOCSIFMEDIA) && !defined(EPIC_NOIFMEDIA)
< int
< epic_ifmedia_change __P((
< struct ifnet * ifp))
---
> /*
> * Set media options.
> */
> static int
> epic_ifmedia_upd(ifp)
> struct ifnet *ifp;
1227c1192,1198
< epic_softc_t *sc = (epic_softc_t *)(ifp->if_softc);
---
> epic_softc_t *sc;
> struct mii_data *mii;
> struct ifmedia *ifm;
>
> sc = ifp->if_softc;
>
> mii = epic_mii_ptr(sc);
1229,1230c1200
< if (IFM_TYPE(sc->ifmedia.ifm_media) != IFM_ETHER)
< return (EINVAL);
---
> ifm = &mii->mii_media;
1232c1202,1203
< if (!(ifp->if_flags & IFF_UP))
---
> /* Do not do anything if interface is not up */
> if(!(ifp->if_flags & IFF_UP))
1235,1237c1206,1213
< epic_stop_activity(sc);
< epic_set_media_speed(sc);
< epic_start_activity(sc);
---
> if((IFM_INST(ifm->ifm_cur->ifm_media) == mii->mii_instance) &&
> (IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_10_2)) {
> /* Call this, to isolate (and powerdown ?) all PHYs */
> mii_mediachg(mii);
>
> /* Select BNC */
> CSR_WRITE_4(sc, MIICFG, MIICFG_SERIAL_ENABLE |
> MIICFG_694_ENABLE | MIICFG_SMI_ENABLE);
1239c1215,1229
< return 0;
---
> /* Update txcon register */
> epic_miibus_statchg(&sc->dev);
>
> return (0);
> } else if(IFM_INST(ifm->ifm_cur->ifm_media) < mii->mii_instance) {
> /* Select MII */
> CSR_WRITE_4(sc, MIICFG, MIICFG_SMI_ENABLE);
>
> /* Give it to miibus... */
> mii_mediachg(mii);
>
> return (0);
> }
>
> return(EINVAL);
1242,1245c1232,1238
< void
< epic_ifmedia_status __P((
< struct ifnet * ifp,
< struct ifmediareq *ifmr))
---
> /*
> * Report current media status.
> */
> static void
> epic_ifmedia_sts(ifp, ifmr)
> struct ifnet *ifp;
> struct ifmediareq *ifmr;
1247,1249c1240,1250
< epic_softc_t *sc = ifp->if_softc;
< u_int32_t bmcr;
< u_int32_t bmsr;
---
> epic_softc_t *sc;
> struct mii_data *mii;
> struct ifmedia *ifm;
>
> sc = ifp->if_softc;
> mii = epic_mii_ptr(sc);
> ifm = &mii->mii_media;
>
> if(!(ifp->if_flags & IFF_UP)) {
> ifmr->ifm_active = IFM_NONE;
> ifmr->ifm_status = 0;
1251d1251
< if (!(ifp->if_flags & IFF_UP))
1252a1253
> }
1254c1255,1266
< bmcr = PHY_READ_2( sc, DP83840_BMCR );
---
> if((IFM_INST(ifm->ifm_cur->ifm_media) == mii->mii_instance) &&
> (IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_10_2)) {
> ifmr->ifm_active = ifm->ifm_cur->ifm_media;
> ifmr->ifm_status = 0;
> } else if(IFM_INST(ifm->ifm_cur->ifm_media) < mii->mii_instance) {
> mii_pollstat(mii);
> ifmr->ifm_active = mii->mii_media_active;
> ifmr->ifm_status = mii->mii_media_status;
> } else {
> ifmr->ifm_active = IFM_NONE;
> ifmr->ifm_status = 0;
> }
1256,1257c1268,1269
< PHY_READ_2( sc, DP83840_BMSR );
< bmsr = PHY_READ_2( sc, DP83840_BMSR );
---
> return;
> }
1259,1260c1271,1279
< ifmr->ifm_active = IFM_ETHER;
< ifmr->ifm_status = IFM_AVALID;
---
> /*
> * Callback routine, called on media change.
> */
> static void
> epic_miibus_statchg(dev)
> struct device* dev;
> {
> epic_softc_t *sc;
> struct mii_data *mii;
1262,1266c1281,1282
< if( !(bmsr & BMSR_LINK_STATUS) ) {
< ifmr->ifm_active |=
< (bmcr&BMCR_AUTONEGOTIATION)?IFM_AUTO:IFM_NONE;
< return;
< }
---
> sc = epic_dev_ptr(dev);
> mii = epic_mii_ptr(sc);
1268,1274c1284
< ifmr->ifm_status |= IFM_ACTIVE;
< ifmr->ifm_active |= (bmcr & BMCR_100MBPS) ? IFM_100_TX : IFM_10_T;
< ifmr->ifm_active |= (bmcr & BMCR_FULL_DUPLEX) ? IFM_FDX : 0;
< if ((sc->txcon & TXCON_LOOPBACK_MODE) == TXCON_LOOPBACK_MODE_INT)
< ifmr->ifm_active |= (IFM_LOOP | IFM_FLAG1);
< else if ((sc->txcon & TXCON_LOOPBACK_MODE) == TXCON_LOOPBACK_MODE_PHY)
< ifmr->ifm_active |= IFM_LOOP;
---
> sc->txcon &= ~(TXCON_LOOPBACK_MODE | TXCON_FULL_DUPLEX);
1275a1286,1322
> /*
> * If we are in full-duplex mode or loopback operation,
> * we need to decouple receiver and transmitter.
> */
> if (mii->mii_media_active & (IFM_FDX | IFM_LOOP))
> sc->txcon |= TXCON_FULL_DUPLEX;
>
> if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX)
> sc->sc_if.if_baudrate = 100000000;
> else
> sc->sc_if.if_baudrate = 10000000;
>
> epic_set_tx_mode(sc);
>
> return;
> }
>
> #if defined(__FreeBSD__)
> static void epic_miibus_mediainit(dev)
> struct device* dev;
> {
> epic_softc_t *sc;
> struct mii_data *mii;
> struct ifmedia *ifm;
> int media;
>
> sc = epic_dev_ptr(dev);
> mii = epic_mii_ptr(sc);
> ifm = &mii->mii_media;
>
> if(CSR_READ_4(sc, MIICFG) & MIICFG_PHY_PRESENT) {
> media = IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, mii->mii_instance);
> printf(EPIC_FORMAT ": serial PHY detected (10Base2/BNC)\n",EPIC_ARGS(sc));
> ifmedia_add(ifm, media, 0, NULL);
> }
>
> return;
1280,1282c1327
< * Reset chip, PHY, allocate rings
< *
< * splimp() invoked here
---
> * Reset chip, allocate rings, and update media.
1284,1286c1329,1331
< int
< epic_init __P((
< epic_softc_t * sc))
---
> static int
> epic_init(sc)
> epic_softc_t *sc;
1289c1334,1335
< int s,i;
---
> struct mii_data *mii;
> int s;
1292a1339,1344
> /* If interface is already running, then we need not do anything */
> if (ifp->if_flags & IFF_RUNNING) {
> splx(s);
> return 0;
> }
> #ifdef __reset
1307a1360,1361
> #endif
> epic_reset( sc );
1338,1339c1392
< INTSTAT_FATAL |
< ((QS6612_OUI == sc->phyid)?INTSTAT_GP2:0) );
---
> INTSTAT_FATAL);
1346,1348d1398
< /* Set media speed mode */
< epic_set_media_speed( sc );
<
1359,1374c1409,1416
< splx(s);
< return 0;
< }
<
< /*
< * Synopsis: calculate and set Rx mode. Chip must be in idle state to
< * access RXCON.
< */
< void
< epic_set_rx_mode(
< epic_softc_t * sc)
< {
< u_int32_t flags = sc->sc_if.if_flags;
< u_int32_t rxcon = RXCON_DEFAULT | RXCON_RECEIVE_MULTICAST_FRAMES | RXCON_RECEIVE_BROADCAST_FRAMES;
<
< rxcon |= (flags & IFF_PROMISC)?RXCON_PROMISCUOUS_MODE:0;
---
> /* Reset all PHYs */
> mii = epic_mii_ptr(sc);
> if (mii->mii_instance) {
> struct mii_softc *miisc;
> for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
> miisc = LIST_NEXT(miisc, mii_list))
> mii_phy_reset(miisc);
> }
1376c1418,1419
< CSR_WRITE_4( sc, RXCON, rxcon );
---
> /* Set appropriate media */
> epic_ifmedia_upd(ifp);
1378,1384c1421
< return;
< }
<
< #if 0
< void
< epic_dump_phy_regs(epic_softc_t *sc)
< {
---
> splx(s);
1386,1394c1423
< printf("BMCR: 0x%04x\n", PHY_READ_2(sc, DP83840_BMCR));
< printf("BMSR: 0x%04x\n", PHY_READ_2(sc, DP83840_BMSR));
< printf("ANAR: 0x%04x\n", PHY_READ_2(sc, DP83840_ANAR));
< printf("LPAR: 0x%04x\n", PHY_READ_2(sc, DP83840_LPAR));
< printf("ANER: 0x%04x\n", PHY_READ_2(sc, DP83840_ANER));
< printf("MCTL: 0x%04x\n", PHY_READ_2(sc, QS6612_MCTL));
< printf("INTSTAT: 0x%04x\n", PHY_READ_2(sc, QS6612_INTSTAT));
< printf("INTMASK: 0x%04x\n", PHY_READ_2(sc, QS6612_INTMASK));
< printf("BPCR: 0x%04x\n", PHY_READ_2(sc, QS6612_BPCR));
---
> return 0;
1396d1424
< #endif
1399c1427
< * Synopsis: Reset PHY and do PHY-special initialization:
---
> * Reset the epic chip
1401,1403c1429,1430
< void
< epic_init_phy __P((
< epic_softc_t * sc))
---
> static void epic_reset(sc)
> epic_softc_t *sc;
1405c1432
< u_int32_t i;
---
> int i;
1407,1417c1434,1436
< /* Reset PHY (We have to take the delay from manual XXX) */
< PHY_WRITE_2(sc, DP83840_BMCR, BMCR_RESET);
< DELAY(10);
< for(i=0;i<0x1000;i++) {
< if( !(PHY_READ_2(sc, DP83840_BMCR) & BMCR_RESET) )
< break;
< DELAY(1);
< }
<
< if( PHY_READ_2(sc, DP83840_BMCR) & BMCR_RESET )
< printf(EPIC_FORMAT ": WARNING! cant reset PHY\n",EPIC_ARGS(sc));
---
> /* Soft reset the chip (we have to power up card before) */
> CSR_WRITE_4( sc, GENCTL, 0 );
> CSR_WRITE_4( sc, GENCTL, GENCTL_SOFT_RESET );
1419,1420c1438,1442
< PHY_WRITE_2(sc, DP83840_BMCR, 0 );
< PHY_WRITE_2(sc, DP83840_BMCR, BMCR_LOOPBACK | BMCR_ISOLATE );
---
> /*
> * Reset takes 15 pci ticks which depends on PCI bus speed.
> * Assuming it >= 33000000 hz, we have wait at least 495e-6 sec.
> */
> DELAY(500);
1422,1435c1444,1445
< switch( sc->phyid ){
< case QS6612_OUI: {
< /* Init QS6612 and EPIC to generate interrupt */
< CSR_WRITE_4(sc, NVCTL, NVCTL_GP1_OUTPUT_ENABLE | NVCTL_GP1);
<
< /* Mask interrupts sources */
< PHY_WRITE_2(sc, QS6612_INTMASK,
< PHY_READ_2(sc, QS6612_INTSTAT) |
< INTMASK_THUNDERLAN | INTSTAT_AN_COMPLETE |
< INTSTAT_LINK_STATUS );
<
< /* Enable QS6612 extended cable length capabilites */
< /* PHY_WRITE_2(sc, QS6612_MCTL, */
< /* PHY_READ_2(sc, QS6612_MCTL) | MCTL_BTEXT); */
---
> /* Wake up */
> CSR_WRITE_4( sc, GENCTL, 0 );
1437,1441c1447,1448
< break;
< }
< default:
< break;
< }
---
> /* Workaround for Application Note 7-15 */
> for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
1443d1449
<
1445,1446c1451,1452
< * Synopsis: Set PHY to media type specified by IFF_LINK* flags or
< * ifmedia structure. Chip must be in idle state to access TXCON.
---
> * Synopsis: calculate and set Rx mode. Chip must be in idle state to
> * access RXCON.
1448,1450c1454,1456
< void
< epic_set_media_speed __P((
< epic_softc_t * sc))
---
> static void
> epic_set_rx_mode(sc)
> epic_softc_t *sc;
1452,1509c1458,1459
< u_int16_t media;
< #if !defined(EPIC_NOIFMEDIA)
< u_int32_t tgtmedia = sc->ifmedia.ifm_cur->ifm_media;
< #endif
<
< epic_init_phy(sc);
<
< #if !defined(EPIC_NOIFMEDIA)
< if( IFM_SUBTYPE(tgtmedia) != IFM_AUTO ){
< /* Clean previous values */
< sc->txcon &= ~(TXCON_LOOPBACK_MODE | TXCON_FULL_DUPLEX);
< media = 0;
<
< /* Set mode */
< media |= (IFM_SUBTYPE(tgtmedia)==IFM_100_TX) ? BMCR_100MBPS : 0;
< if (tgtmedia & IFM_FDX) {
< media |= BMCR_FULL_DUPLEX;
< sc->txcon |= TXCON_FULL_DUPLEX;
< }
< if (tgtmedia & IFM_LOOP) {
< if (tgtmedia & IFM_FLAG1)
< sc->txcon |= TXCON_LOOPBACK_MODE_INT;
< else {
< media |= BMCR_LOOPBACK | BMCR_ISOLATE;
< sc->txcon |= TXCON_LOOPBACK_MODE_PHY;
< }
< }
<
< sc->sc_if.if_baudrate =
< (IFM_SUBTYPE(tgtmedia)==IFM_100_TX)?100000000:10000000;
<
< PHY_WRITE_2( sc, DP83840_BMCR, media );
< }
< #else /* EPIC_NOIFMEDIA */
< struct ifnet *ifp = &sc->sc_if;
<
< if( ifp->if_flags & IFF_LINK0 ) {
< /* Set mode */
< media = 0;
< media|= (ifp->if_flags & IFF_LINK2) ? BMCR_100MBPS : 0;
< media|= (ifp->if_flags & IFF_LINK1) ? BMCR_FULL_DUPLEX : 0;
<
< sc->sc_if.if_baudrate =
< (ifp->if_flags & IFF_LINK2)?100000000:10000000;
<
< PHY_WRITE_2( sc, DP83840_BMCR, media );
<
< if( ifp->if_flags & IFF_LINK2 ) sc->txcon |= TXCON_FULL_DUPLEX;
< else sc->txcon &= ~TXCON_FULL_DUPLEX;
<
< CSR_WRITE_4( sc, TXCON, sc->txcon );
< }
< #endif /* !EPIC_NOIFMEDIA */
< else {
< sc->sc_if.if_baudrate = 100000000;
<
< sc->txcon &= ~TXCON_FULL_DUPLEX;
< CSR_WRITE_4(sc, TXCON, sc->txcon);
---
> u_int32_t flags = sc->sc_if.if_flags;
> u_int32_t rxcon = RXCON_DEFAULT;
1511,1530c1461
< /* Set and restart autoneg */
< PHY_WRITE_2(sc, DP83840_BMCR, BMCR_AUTONEGOTIATION );
< PHY_WRITE_2(sc, DP83840_BMCR,
< BMCR_AUTONEGOTIATION | BMCR_RESTART_AUTONEG);
<
< /* If it is not QS6612 PHY, try to get result of autoneg. */
< if( QS6612_OUI != sc->phyid ) {
< /* Wait 3 seconds for the autoneg to finish
< * This is the recommended time from the DP83840A data
< * sheet Section 7.1
< */
< DELAY(3000000);
<
< if( epic_autoneg(sc) == EPIC_FULL_DUPLEX ) {
< sc->txcon |= TXCON_FULL_DUPLEX;
< CSR_WRITE_4(sc, TXCON, sc->txcon);
< }
< }
< /* Else it will be done when GP2 int occured */
< }
---
> rxcon |= (flags & IFF_PROMISC) ? RXCON_PROMISCUOUS_MODE : 0;
1532c1463
< epic_set_tx_mode(sc);
---
> CSR_WRITE_4( sc, RXCON, rxcon );
1538,1615c1469,1470
< * This functions get results of the autoneg processes of the phy
< * It implements the workaround that is described in section 7.2 & 7.3 of the
< * DP83840A data sheet
< * http://www.national.com/ds/DP/DP83840A.pdf
< */
< int
< epic_autoneg(
< epic_softc_t * sc)
< {
< u_int16_t media;
< u_int16_t i;
<
< /* BMSR must be read twice to update the link status bit
< * since that bit is a latch bit
< */
< PHY_READ_2( sc, DP83840_BMSR);
< i = PHY_READ_2( sc, DP83840_BMSR);
<
< if ((i & BMSR_LINK_STATUS) && (i & BMSR_AUTONEG_COMPLETE)){
< i = PHY_READ_2( sc, DP83840_LPAR );
<
< if ( i & (ANAR_100_TX_FD|ANAR_10_FD) )
< return EPIC_FULL_DUPLEX;
< else
< return EPIC_HALF_DUPLEX;
< } else {
< /*Auto-negotiation or link status is not 1
< Thus the auto-negotiation failed and one
< must take other means to fix it.
< */
<
< /* ANER must be read twice to get the correct reading for the
< * Multiple link fault bit -- it is a latched bit
< */
< PHY_READ_2( sc, DP83840_ANER );
< i = PHY_READ_2( sc, DP83840_ANER );
<
< if ( i & ANER_MULTIPLE_LINK_FAULT ) {
< /* it can be forced to 100Mb/s Half-Duplex */
< media = PHY_READ_2( sc, DP83840_BMCR );
< media &= ~(BMCR_AUTONEGOTIATION | BMCR_FULL_DUPLEX);
< media |= BMCR_100MBPS;
< PHY_WRITE_2( sc, DP83840_BMCR, media );
<
< /* read BMSR again to determine link status */
< PHY_READ_2( sc, DP83840_BMSR );
< i=PHY_READ_2( sc, DP83840_BMSR );
<
< if (i & BMSR_LINK_STATUS){
< /* port is linked to the non Auto-Negotiation
< * 100Mbs partner.
< */
< return EPIC_HALF_DUPLEX;
< }
< else {
< media = PHY_READ_2( sc, DP83840_BMCR);
< media &= ~(BMCR_AUTONEGOTIATION | BMCR_FULL_DUPLEX | BMCR_100MBPS);
< PHY_WRITE_2( sc, DP83840_BMCR, media);
< PHY_READ_2( sc, DP83840_BMSR );
< i = PHY_READ_2( sc, DP83840_BMSR );
<
< if (i & BMSR_LINK_STATUS) {
< /*port is linked to the non
< * Auto-Negotiation10Mbs partner
< */
< return EPIC_HALF_DUPLEX;
< }
< }
< }
< /* If we get here we are most likely not connected
< * so lets default it to half duplex
< */
< return EPIC_HALF_DUPLEX;
< }
<
< }
<
< /*
---
> * Synopsis: Set transmit control register. Chip must be in idle state to
> * access TXCON.
1617,1619c1472,1474
< void
< epic_set_tx_mode (
< epic_softc_t *sc )
---
> static void
> epic_set_tx_mode(sc)
> epic_softc_t *sc;
1620a1476,1477
> if (sc->txcon & TXCON_EARLY_TRANSMIT_ENABLE)
> CSR_WRITE_4 (sc, ETXTHR, sc->tx_threshold);
1622,1625c1479
< if( sc->txcon & TXCON_EARLY_TRANSMIT_ENABLE )
< CSR_WRITE_4( sc, ETXTHR, sc->tx_threshold );
<
< CSR_WRITE_4( sc, TXCON, sc->txcon );
---
> CSR_WRITE_4 (sc, TXCON, sc->txcon);
1636,1638c1490,1492
< void
< epic_set_mc_table (
< epic_softc_t * sc)
---
> static void
> epic_set_mc_table(sc)
> epic_softc_t *sc;
1656,1658c1510,1512
< void
< epic_start_activity __P((
< epic_softc_t * sc))
---
> static void
> epic_start_activity(sc)
> epic_softc_t *sc;
1660,1664c1514,1518
< /* Start rx process */
< CSR_WRITE_4(sc, COMMAND,
< COMMAND_RXQUEUED | COMMAND_START_RX |
< (sc->pending_txs?COMMAND_TXQUEUED:0));
< dprintf((EPIC_FORMAT ": activity started\n",EPIC_ARGS(sc)));
---
> /* Start rx process */
> CSR_WRITE_4(sc, COMMAND,
> COMMAND_RXQUEUED | COMMAND_START_RX |
> (sc->pending_txs?COMMAND_TXQUEUED:0));
> dprintf((EPIC_FORMAT ": activity started\n",EPIC_ARGS(sc)));
1671,1673c1525,1527
< void
< epic_stop_activity __P((
< epic_softc_t * sc))
---
> static void
> epic_stop_activity(sc)
> epic_softc_t *sc;
1765,1766d1618
< *
< * splimp() invoked here
1768,1770c1620,1622
< void
< epic_stop __P((
< epic_softc_t * sc))
---
> static void
> epic_stop(sc)
> epic_softc_t *sc;
1805,1807c1657,1659
< void
< epic_free_rings __P((
< epic_softc_t * sc))
---
> static void
> epic_free_rings(sc)
> epic_softc_t *sc;
1841,1842c1693,1696
< int
< epic_init_rings(epic_softc_t * sc){
---
> static int
> epic_init_rings(sc)
> epic_softc_t *sc;
> {
1891,1893c1745,1748
< void epic_write_eepromreg __P((
< epic_softc_t *sc,
< u_int8_t val))
---
> static void
> epic_write_eepromreg(sc, val)
> epic_softc_t *sc;
> u_int8_t val;
1905,1907c1760,1762
< u_int8_t
< epic_read_eepromreg __P((
< epic_softc_t *sc))
---
> static u_int8_t
> epic_read_eepromreg(sc)
> epic_softc_t *sc;
1909c1764
< return CSR_READ_1( sc,EECTL );
---
> return CSR_READ_1(sc, EECTL);
1912,1915c1767,1770
< u_int8_t
< epic_eeprom_clock __P((
< epic_softc_t *sc,
< u_int8_t val))
---
> static u_int8_t
> epic_eeprom_clock(sc, val)
> epic_softc_t *sc;
> u_int8_t val;
1924,1927c1779,1782
< void
< epic_output_eepromw __P((
< epic_softc_t * sc,
< u_int16_t val))
---
> static void
> epic_output_eepromw(sc, val)
> epic_softc_t *sc;
> u_int16_t val;
1936,1938c1791,1793
< u_int16_t
< epic_input_eepromw __P((
< epic_softc_t *sc))
---
> static u_int16_t
> epic_input_eepromw(sc)
> epic_softc_t *sc;
1953,1956c1808,1811
< int
< epic_read_eeprom __P((
< epic_softc_t *sc,
< u_int16_t loc))
---
> static int
> epic_read_eeprom(sc, loc)
> epic_softc_t *sc;
> u_int16_t loc;
1977,1980c1832,1838
< u_int16_t
< epic_read_phy_register __P((
< epic_softc_t *sc,
< u_int16_t loc))
---
> /*
> * Here goes MII read/write routines
> */
> static int
> epic_read_phy_reg(sc, phy, reg)
> epic_softc_t *sc;
> int phy, reg;
1984c1842
< CSR_WRITE_4( sc, MIICTL, ((loc << 4) | 0x0601) );
---
> CSR_WRITE_4 (sc, MIICTL, ((reg << 4) | (phy << 9) | 0x01));
1987c1845
< if( !(CSR_READ_4( sc, MIICTL )&1) ) break;
---
> if( !(CSR_READ_4(sc, MIICTL) & 0x01) ) break;
1991c1849
< return CSR_READ_4( sc, MIIDATA );
---
> return (CSR_READ_4 (sc, MIIDATA));
1994,1998c1852,1855
< void
< epic_write_phy_register __P((
< epic_softc_t * sc,
< u_int16_t loc,
< u_int16_t val))
---
> static void
> epic_write_phy_reg(sc, phy, reg, val)
> epic_softc_t *sc;
> int phy, reg, val;
2002,2003c1859,1860
< CSR_WRITE_4( sc, MIIDATA, val );
< CSR_WRITE_4( sc, MIICTL, ((loc << 4) | 0x0602) );
---
> CSR_WRITE_4 (sc, MIIDATA, val);
> CSR_WRITE_4 (sc, MIICTL, ((reg << 4) | (phy << 9) | 0x02));
2005,2006c1862,1863
< for( i=0;i<0x100;i++) {
< if( !(CSR_READ_4( sc, MIICTL )&2) ) break;
---
> for(i=0;i<0x100;i++) {
> if( !(CSR_READ_4(sc, MIICTL) & 0x02) ) break;
2013,2015c1870,1873
< void
< epic_dump_state __P((
< epic_softc_t * sc))
---
> static int
> epic_miibus_readreg(dev, phy, reg)
> struct device* dev;
> int phy, reg;
2017,2046c1875,1895
< int j;
< struct epic_tx_desc *tdesc;
< struct epic_rx_desc *rdesc;
< printf(EPIC_FORMAT ": cur_rx: %d, pending_txs: %d, dirty_tx: %d, cur_tx: %d\n", EPIC_ARGS(sc),sc->cur_rx,sc->pending_txs,sc->dirty_tx,sc->cur_tx);
< printf(EPIC_FORMAT ": COMMAND: 0x%08x, INTSTAT: 0x%08x\n",EPIC_ARGS(sc),CSR_READ_4(sc,COMMAND),CSR_READ_4(sc,INTSTAT));
< printf(EPIC_FORMAT ": PRCDAR: 0x%08x, PTCDAR: 0x%08x\n",EPIC_ARGS(sc),CSR_READ_4(sc,PRCDAR),CSR_READ_4(sc,PTCDAR));
< printf(EPIC_FORMAT ": dumping rx descriptors\n",EPIC_ARGS(sc));
< for(j=0;j<RX_RING_SIZE;j++){
< rdesc = sc->rx_desc + j;
< printf("desc%d: %4d 0x%04x, 0x%08x, %4d, 0x%08x\n",
< j,
< rdesc->rxlength,rdesc->status,
< rdesc->bufaddr,
< rdesc->buflength,
< rdesc->next
< );
< }
< printf(EPIC_FORMAT ": dumping tx descriptors\n",EPIC_ARGS(sc));
< for(j=0;j<TX_RING_SIZE;j++){
< tdesc = sc->tx_desc + j;
< printf(
< "desc%d: %4d 0x%04x, 0x%08lx, 0x%04x %4u, 0x%08lx, mbuf: %p\n",
< j,
< tdesc->txlength,tdesc->status,
< (u_long)tdesc->bufaddr,
< tdesc->control,tdesc->buflength,
< (u_long)tdesc->next,
< (void *)sc->tx_buffer[j].mbuf
< );
< }
---
> epic_softc_t *sc;
>
> sc = epic_dev_ptr(dev);
>
> return (PHY_READ_2(sc, phy, reg));
> }
>
> static EPIC_MIIBUS_WRITEREG_RET_TYPE
> epic_miibus_writereg(dev, phy, reg, data)
> struct device* dev;
> int phy, reg, data;
> {
> epic_softc_t *sc;
>
> sc = epic_dev_ptr(dev);
>
> PHY_WRITE_2(sc, phy, reg, data);
>
> #if !defined(__OpenBSD__)
> return (0);
> #endif
2048d1896
< #endif /* NPCI > 0 */
Index: if_txvar.h
===================================================================
RCS file: /cvs/src/sys/dev/pci/if_txvar.h,v
retrieving revision 1.7
diff -r1.7 if_txvar.h
2c2
< /* $FreeBSD: src/sys/pci/if_txvar.h,v 1.5 1999/10/29 09:56:52 semenu Exp $ */
---
> /* $FreeBSD: src/sys/pci/if_txvar.h,v 1.7 2000/06/21 19:19:49 semenu Exp $ */
32a33,36
> /*#define EPIC_DEBUG 1*/
> /*#define EPIC_USEIOSPACE 1*/
> #define EARLY_RX 1
>
47,48d50
< #define EPIC_FULL_DUPLEX 1
< #define EPIC_HALF_DUPLEX 0
50c52,60
< #define EPIC_LINK_DOWN 0x00000001
---
>
> /* PCI aux configuration registers */
> #if defined(__FreeBSD__)
> #define PCIR_BASEIO (PCIR_MAPS + 0x0) /* Base IO Address */
> #define PCIR_BASEMEM (PCIR_MAPS + 0x4) /* Base Memory Address */
> #else /* __OpenBSD__ */
> #define PCI_BASEIO (PCI_MAPS + 0x0) /* Base IO Address */
> #define PCI_BASEMEM (PCI_MAPS + 0x4) /* Base Memory Address */
> #endif /* __FreeBSD__ */
54,73c64
< #define CHIPID_83C170 0x0005
< #define PCI_VENDORID(x) ((x) & 0xFFFF)
< #define PCI_CHIPID(x) (((x) >> 16) & 0xFFFF)
<
< /* PCI configuration */
< #define PCI_CFID 0x00 /* Configuration ID */
< #define PCI_CFCS 0x04 /* Configurtion Command/Status */
< #define PCI_CFRV 0x08 /* Configuration Revision */
< #define PCI_CFLT 0x0c /* Configuration Latency Timer */
< #define PCI_CBIO 0x10 /* Configuration Base IO Address */
< #define PCI_CBMA 0x14 /* Configuration Base Memory Address */
< #define PCI_CFIT 0x3c /* Configuration Interrupt */
< #define PCI_CFDA 0x40 /* Configuration Driver Area */
<
< #define PCI_CFCS_IOEN 0x0001 /* IO Space Enable */
< #define PCI_CFCS_MAEN 0x0002 /* Memory Space Enable */
< #define PCI_CFCS_BMEN 0x0004 /* Bus Master Enable */
<
< #define PCI_CONF_WRITE(r, v) pci_conf_write(config_id, (r), (v))
< #define PCI_CONF_READ(r) pci_conf_read(config_id, (r))
---
> #define SMC_DEVICEID_83C170 0x0005
116,118d106
< /* Tx threshold */
< #define TX_FIFO_THRESH 0x80 /* 0x40 or 0x10 */
<
196a185,188
> #define MIICFG_SERIAL_ENABLE 0x00000001
> #define MIICFG_694_ENABLE 0x00000002
> #define MIICFG_694_STATUS 0x00000004
> #define MIICFG_PHY_PRESENT 0x00000008
200a193,195
> /*
> * Some default values
> */
202c197
< #define TRANSMIT_THRESHOLD 0x80
---
> #define TRANSMIT_THRESHOLD 0x300
205c200,201
< #define RXCON_DEFAULT (RXCON_EARLY_RECEIVE_ENABLE | RXCON_SAVE_ERRORED_PACKETS)
---
> #define RXCON_EARLY (RXCON_EARLY_RECEIVE_ENABLE | \
> RXCON_SAVE_ERRORED_PACKETS)
207c203
< #define RXCON_DEFAULT (0)
---
> #define RXCON_EARLY (0)
209,250d204
< /*
< * National Semiconductor's DP83840A Registers and bits
< */
< #define DP83840_OUI 0x080017
< #define DP83840_BMCR 0x00 /* Control register */
< #define DP83840_BMSR 0x01 /* Status rgister */
< #define DP83840_ANAR 0x04 /* Autonegotiation advertising register */
< #define DP83840_LPAR 0x05 /* Link Partner Ability register */
< #define DP83840_ANER 0x06 /* Auto-Negotiation Expansion Register */
< #define DP83840_PAR 0x19 /* PHY Address Register */
< #define DP83840_PHYIDR1 0x02
< #define DP83840_PHYIDR2 0x03
<
< #define BMCR_RESET 0x8000
< #define BMCR_LOOPBACK 0x4000
< #define BMCR_100MBPS 0x2000 /* 10/100 Mbps */
< #define BMCR_AUTONEGOTIATION 0x1000 /* ON/OFF */
< #define BMCR_POWERDOWN 0x0800
< #define BMCR_ISOLATE 0x0400
< #define BMCR_RESTART_AUTONEG 0x0200
< #define BMCR_FULL_DUPLEX 0x0100
< #define BMCR_COL_TEST 0x0080
<
< #define BMSR_100BASE_T4 0x8000
< #define BMSR_100BASE_TX_FD 0x4000
< #define BMSR_100BASE_TX 0x2000
< #define BMSR_10BASE_T_FD 0x1000
< #define BMSR_10BASE_T 0x0800
< #define BMSR_AUTONEG_COMPLETE 0x0020
< #define BMSR_AUTONEG_ABLE 0x0008
< #define BMSR_LINK_STATUS 0x0004
<
< #define PAR_FULL_DUPLEX 0x0400
<
< #define ANER_MULTIPLE_LINK_FAULT 0x10
<
< /* ANAR and LPAR have the same bits, define them only once */
< #define ANAR_10 0x0020
< #define ANAR_10_FD 0x0040
< #define ANAR_100_TX 0x0080
< #define ANAR_100_TX_FD 0x0100
< #define ANAR_100_T4 0x0200
252,274c206,208
< /*
< * Quality Semiconductor's QS6612 registers and bits
< */
< #define QS6612_OUI 0x006051
< #define QS6612_MCTL 17
< #define QS6612_INTSTAT 29
< #define QS6612_INTMASK 30
< #define QS6612_BPCR 31
<
< #define MCTL_T4_PRESENT 0x1000 /* External T4 Enabled, ignored */
< /* if AutoNeg is enabled */
< #define MCTL_BTEXT 0x0800 /* Reduces 10baset squelch level */
< /* for extended cable length */
<
< #define INTSTAT_AN_COMPLETE 0x40 /* Autonegotiation complete */
< #define INTSTAT_RF_DETECTED 0x20 /* Remote Fault detected */
< #define INTSTAT_LINK_STATUS 0x10 /* Link status changed */
< #define INTSTAT_AN_LP_ACK 0x08 /* Autoneg. LP Acknoledge */
< #define INTSTAT_PD_FAULT 0x04 /* Parallel Detection Fault */
< #define INTSTAT_AN_PAGE 0x04 /* Autoneg. Page Received */
< #define INTSTAT_RE_CNT_FULL 0x01 /* Receive Error Counter Full */
<
< #define INTMASK_THUNDERLAN 0x8000 /* Enable interrupts */
---
> #define RXCON_DEFAULT (RXCON_EARLY | \
> RXCON_RECEIVE_MULTICAST_FRAMES | \
> RXCON_RECEIVE_BROADCAST_FRAMES)
326c260,264
< /* Driver status structure */
---
> /*
> * Driver status structure
> * There are macros to handle the access of Free|Open specific fields.
> */
>
329c267,281
< struct device sc_dev;
---
> struct device dev;
>
> struct arpcom arpcom;
>
> mii_data_t miibus;
> #else /* __FreeBSD__ */
> struct resource *res;
> struct resource *irq;
>
> device_t miibus;
> device_t dev;
> struct callout_handle stat_ch;
>
> u_int32_t unit;
> #endif
333,344c285
< #else /* __FreeBSD__ */
< #if defined(EPIC_USEIOSPACE)
< u_int32_t iobase;
< #else
< caddr_t csr;
< #endif
< #endif
< #if !defined(EPIC_NOIFMEDIA)
< struct ifmedia ifmedia;
< #endif
< struct arpcom arpcom;
< u_int32_t unit;
---
>
363a305,316
> struct epic_type {
> u_int16_t ven_id;
> u_int16_t dev_id;
> char *name;
> };
>
> #if defined(EPIC_DEBUG)
> #define dprintf(a) printf a
> #else
> #define dprintf(a)
> #endif
>
367,395c320
< #define sc_if arpcom.ac_if
< #define sc_macaddr arpcom.ac_enaddr
< #if defined(EPIC_USEIOSPACE)
< #define CSR_WRITE_4(sc,reg,val) \
< outl( (sc)->iobase + (u_int32_t)(reg), (val) )
< #define CSR_WRITE_2(sc,reg,val) \
< outw( (sc)->iobase + (u_int32_t)(reg), (val) )
< #define CSR_WRITE_1(sc,reg,val) \
< outb( (sc)->iobase + (u_int32_t)(reg), (val) )
< #define CSR_READ_4(sc,reg) \
< inl( (sc)->iobase + (u_int32_t)(reg) )
< #define CSR_READ_2(sc,reg) \
< inw( (sc)->iobase + (u_int32_t)(reg) )
< #define CSR_READ_1(sc,reg) \
< inb( (sc)->iobase + (u_int32_t)(reg) )
< #else
< #define CSR_WRITE_1(sc,reg,val) \
< ((*(volatile u_int8_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int8_t)(val))
< #define CSR_WRITE_2(sc,reg,val) \
< ((*(volatile u_int16_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int16_t)(val))
< #define CSR_WRITE_4(sc,reg,val) \
< ((*(volatile u_int32_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int32_t)(val))
< #define CSR_READ_1(sc,reg) \
< (*(volatile u_int8_t*)((sc)->csr + (u_int32_t)(reg)))
< #define CSR_READ_2(sc,reg) \
< (*(volatile u_int16_t*)((sc)->csr + (u_int32_t)(reg)))
< #define CSR_READ_4(sc,reg) \
< (*(volatile u_int32_t*)((sc)->csr + (u_int32_t)(reg)))
< #endif
---
> #define EPIC_BPFTAP_ARG(ifp) ifp
398,399c323,327
< #define EPIC_ARGS(sc) (sc->sc_dev.dv_xname)
< #define sc_if arpcom.ac_if
---
> #define EPIC_ARGS(sc) (sc->dev.dv_xname)
> #define EPIC_BPFTAP_ARG(ifp) (ifp)->if_bpf
> #endif
>
> #define sc_if arpcom.ac_if
400a329
>
413d341
< #endif
415,416c343,378
< #define PHY_READ_2(sc,reg) epic_read_phy_register(sc,reg)
< #define PHY_WRITE_2(sc,reg,val) epic_write_phy_register(sc,reg,val)
---
> #define PHY_READ_2(sc,phy,reg) \
> epic_read_phy_reg((sc),(phy),(reg))
> #define PHY_WRITE_2(sc,phy,reg,val) \
> epic_write_phy_reg((sc),(phy),(reg),(val))
>
> /* Macro to get either mbuf cluster or nothing */
> #define EPIC_MGETCLUSTER(m) \
> { MGETHDR((m),M_DONTWAIT,MT_DATA); \
> if (m) { \
> MCLGET((m),M_DONTWAIT); \
> if( 0 == ((m)->m_flags & M_EXT) ) { \
> m_freem(m); \
> (m) = NULL; \
> } \
> } \
> }
> /*
> * Platform Independant Field Accessors
> */
> #if defined(__OpenBSD__)
>
> #define epic_dev(sc) (*sc)
> #define epic_dev_ptr(sc) (void*)(sc)
>
> #define epic_mii(sc) (sc->miibus)
> #define epic_mii_ptr(sc) (&sc->miibus)
>
> #else
>
> #define epic_dev(dev) (*(device_get_softc(dev))
> #define epic_dev_ptr(dev) (device_get_softc(dev))
>
> #define epic_mii(sc) (*(device_get_softc(sc->miibus))
> #define epic_mii_ptr(sc) (device_get_softc(sc->miibus))
>
> #endif
Index: files.pci
===================================================================
RCS file: /cvs/src/sys/dev/pci/files.pci,v
retrieving revision 1.84
diff -r1.84 files.pci
214c214
< device tx: ether, ifnet, ifmedia
---
> device tx: ether, ifnet, mii, ifmedia
>Audit-Trail:
>Unformatted: